A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

作者：Kaviani Kambiz^*; Wu Ting; Wei Jason; Amirkhany Amir; Shen Jie; Chin T J; Thakkar Chintan; Beyene Wendemagegnehu T; Chan Norman; Chen Catherine; Chuang Bing Ren; Dressler Deborah; Gadde Vijay P; Hekmat Mohammad; Ho Eugene; Huang Charlie; Phuong Le; Mahabaleshwara; Madden Chris; Mishra Navin Kumar; Raghavan Lenesh; Saito Keisuke; Schmitt Ralf; Secker Dave; Shi Xudong; Fazeel Shuaeb; Srinivas Gundlapalli Shanmukha; Zhang Steve; Tran Chanh; Vaidyanath Arun

来源：IEEE Journal of Solid-State Circuits, 2012, 47(4): 926-937.

DOI：10.1109/JSSC.2012.2185370

• Calibration
• clocking
• DDR
• decision feedback equalization
• GDDR
• high-voltage protection
• multi-standard memory interface
• multi-VCO PLL
• offset cancellation
• predictive DFE
• quadrature generator

This paper describes a tri-modal asymmetric bidirectional differential memory interface that supports data rates of up to 20 Gbps over 3 '' FR4 PCB channels while achieving power efficiency of 6.1 mW/Gbps at full speed. The interface also accommodates single-ended standard DDR3 and GDDR5 signaling at 1.6-Gbps and 6.4-Gbps operations, respectively, without package change. The compact, low-power and high-speed tri-modal interface is enabled by substantial reuse of the circuit elements among various signaling modes, particularly in the wide-band clock generation and distribution system and the multi-modal driver output stage, as well as the use of fast equalization for post-cursor inter-symbol interference (ISI) mitigation. In the high-speed differential mode, the system utilizes a 1-tap transmit equalizer during a WRITE operation to the memory. In contrast, during a memory READ operation, it employs a linear equalizer (LEQ) with 3 dB of peaking as well as a calibrated high-speed 1-tap predictive decision feedback equalizer (prDFE), while no transmitter equalization is assumed for the memory. The prototype tri-modal interface implemented in a 40-nm CMOS process, consists of 16 data links and achieves more than 2.5 x energy-efficient memory transactions at 16 Gbps compared to a previous single-mode generation.

• 出版日期2012-4