摘要

This article proposes a divide-by-3 frequency divider (FD) with quadrature outputs fabricated in the 0.18-mu m CMOS technology. The current reuse and the back-gate coupling techniques are adopted. Measured results show that the free-running frequency is from 1.173 to 1.25 GHz. The proposed FD can cover the input frequency from 3.51 to 3.8 GHz at the incident power of -3 dBm.

  • 出版日期2010-2