A 1-mu W 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

作者：Huang Guan Ying^*; Chang Soon Jyh; Liu Chun Cheng; Lin Ying Zu

来源：IEEE Journal of Solid-State Circuits, 2012, 47(11): 2783-2795.

DOI：10.1109/JSSC.2012.2217635

• Bypass window SAR ADC
• incomplete settling tolerance
• low power ADC
• SAR ADC
• successive approximation analog-to-digital converter

This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small The power consumptions of the capacitive digital-to-analog converter (DAC), latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-mu m 1P6M CMOS technology. At a 0.6-V supply voltage and a 200-kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 57.97 dB and consumes 1.04 mu W, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm(2).

• 出版日期2012-11