A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

作者：Ngoc Hung Nguyen; Khan Sheraz Ali; Kim Cheol Hong; Kim Jong Myon^*

来源：Microprocessors and Microsystems, 2018, 60: 96-106.

DOI：10.1016/j.micpro.2018.04.003

• FFT
• Radix-2 DIF
• DDC architecture
• Parallel-Pipelined
• CORDIC algorithm
• CSDBE
• FPGA

The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems (DSPs); hence, the development of a high-performance and resource-efficient FFT processor that conforms to the processing and precision requirements of real-time signal processing is highly desirable. We propose an FFT processor for field programmable gate array (FPGA) devices, based on the radix-2-decimation-in-frequency (R2DIF) algorithm. An appropriately modified parallel double-path delay commutator (DDC) architecture for radix-2 with continuous dual-input and dual-output streams (CoDIDOS) is proposed to increase throughput and reduce latency in FFT computation. The chip-area of the proposed design is reduced by decreasing the memory footprint of the complex twiddle factor multipliers. A multiplication scheme based on a combination of the unrolled coordinate rotation digital computer (CORDIC) and the canonical signed digit-based binary expression (CSDBE) is used to multiply the complex twiddle factors without requiring memory blocks for their storage. The CSDBE technique is proposed to optimize the multiplication of constants in the architecture. The proposed FFT processor is implemented as an intellectual property (IP) core and tested on a Xilinx Virtex-7 FPGA. Experimental results confirm that the proposed design improves the speed, latency, throughput, accuracy, and resource utilization of computation on FPGA devices over existing designs.

• 出版日期2018-7