A robust novel technique for SPICE simulation of ESD snap-back characteristics

作者：Jiao Chao^*; Yu Zhiping

来源：Chinese Journal of Electronics, 2008, 17(1): 71-74.

• ElectoStatic discharge (ESD)
• SPICE (Simulation program with integrated circuit emphasis)
• simulation
• snap-back
• gate-grounded NMOS (GGNMOS)
• gate-coupled NMOS (GCNMOS)
• compact model

This paper presents a robust and novel technique for the circuit simulation of ESD (ElectroStatic discharge) snap-back characteristics. A new linearization scheme by introducing current as independent variable for the avalanche current model in ESD evaluation shows a good convergence behavior during ESD stress simulation. This technique is compatible with the traditional circuit simulator based on the Modified nodal analysis (MNA) like SPICE. We have implemented the well known Amerasekera's ESD MOSFET model in SPICE3f5. The commonly used ESD protection configurations such as GGNMOS (Gate-grounded NMOS) and GCNMOS (Gate-coupled NMOS) are simulated and the simulation results demonstrated the good convergence behavior of this new technique.

• 出版日期2008-1
• 单位清华大学