A Multiplexed Low Power and High Linearity Cascaded Phase Interpolator Design

作者：Kong, Yitong; Ding, Li; Jin, Jing^*

来源：14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018-10-31 To 2018-11-03.

DOI：10.1109/icsict.2018.8565646

In this paper, a novel 14GHz phase interpolator (P1) circuit is presented. It consists of two main parts: trigonometric stage and linear stage. This two-stage cascaded structure is chosen to achieve high linearity. For the purpose of low power, the trigonometric stage is added with extra switches and when the part of circuit is not working, the corresponding switches are off. By this way, the power consumption is reduced. And at the same time, the current-steering DAC blocks of the following stage can be multiplexed because of the former ON-or-OFF control. To achieve high linearity, the linear stage is applied with a novel separate current-steering DAC and the improved results are shown in both theory and practice. The PI is designed in 28nm CMOS technology and gives a differential nonlinearity (in LSB) of 20.6% while consuming only 2.8mW from a 0.9V voltage supply.

• 出版日期2018
• 单位上海交通大学