An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

作者：Soltani Abolfazl^*; Sharifian Saeed

来源：Microprocessors and Microsystems, 2015, 39(7): 480-493.

DOI：10.1016/j.micpro.2015.07.005

• Advanced encryption standard
• Loop-unrolling
• Pipelining
• Finite field
• High throughput
• FPGA

AES (Advanced Encryption Standard) is one of the most popular symmetric key encryption algorithms. S-box (Substitution block) is main block in AES. In contrast to many previous works which have employed only one of memory or non-memory based approaches to implement S-box, we propose efficient methods by combining these approaches. We perform area-delay efficient multipliers and multiplicative inverters in GF(2(8)). We employ loop-unrolling, fully pipelining, and sub-pipelining techniques in all proposed methods. Moreover, we insert registers of pipelining in optimal placements. These reasons demonstrate that proposed methods not only try to keep the advantages of previous works but also try to decrease their disadvantages. By using above techniques, we propose three high-throughput AES implementations in ECB mode and one ultra-high throughput AES implementation in CTR mode. Our AES implementations in ECB mode using Xilinx Virtex-5 (XC5VLX85-FF676-3) and Virtex-6 (XC6VLX240T-FF784-3) FPGAs achieve high throughputs of 82.4 Gbps and 102.9 Gbps and maximum operational frequencies of 644.33 MHz and 803.98 MHz respectively. Compared to the best previous works, these implementations improve data throughput by 11.85% and 71.7%. Our AES implementation in CTR mode on Xilinx Virtex-6 (XC6VLX240T-FF784-3) FPGA achieves a high throughput of 260.15 Gbps and maximum operational frequency of 508.104 MHz.

• 出版日期2015-10