A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC

作者：Miro Panades Ivan^*; Beigne Edith; Thonnart Yvain; Alacoque Laurent; Vivet Pascal; Lesecq Suzanne; Puschini Diego; Molnos Anca; Thabet Farhat; Tain Benoit; Ben Chehida Karim; Engels Sylvain; Wilson Robin; Fuin Didier

来源：IEEE Journal of Solid-State Circuits, 2014, 49(7): 1475-1486.

DOI：10.1109/JSSC.2014.2317137

• Adaptive voltage and frequency scaling (AVFS)
• chip multiprocessor
• energy efficiency
• globally asynchronous locally synchronous (GALS)

In order to optimize global energy efficiency in the context of dynamic process, voltage and temperature variations in advanced nodes, a fine-grain adaptive voltage and frequency scaling architecture is proposed for multiprocessor systems-on-chip (MPSoC), where each processing element is an independent voltage-frequency island. This architecture has been implemented on a 32 nm globally asynchronous locally-synchronous MPSoC. It shows up to 18.2% energy gains thanks to local adaptability compared with a global dynamic voltage and frequency scaling approach using 25% timing margins between slow and nominal process, by reducing margins to 60 ps of the real process. These gains are obtained for a total area overhead of 10% including local frequency/voltage actuators, sensors, and digital controller.

• 出版日期2014-7
• 单位中国地震局