A Continuous-Time Sturdy-MASH Delta Sigma Modulator in 28 nm CMOS

作者：Yoon Do Yeon^*; Ho Stacy; Lee Hae Seung

来源：IEEE Journal of Solid-State Circuits, 2015, 50(12): 2880-2890.

DOI：10.1109/JSSC.2015.2466459

• Analog-to-digital converter (ADC)
• analog delay
• continuous-time (CT)
• delta-sigma
• multi-stage noise-shaping

This paper presents a practical way to achieve both wide signal bandwidth and high dynamic range in a continuous-time (CT) delta-sigma modulator. Quantization noise is suppressed aggressively by increasing the effective order of the noise transfer function based on a sturdy multi-stage noise-shaping (SMASH) architecture. The proposed CT SMASH architecture has a much wider signal bandwidth which was limited in the discrete-time (DT) SMASH architecture due to the inherent sampling frequency limitation of DT implementation. Furthermore, the proposed CT SMASH architecture provides better quantization noise suppression by more completely canceling the quantization noise from the 1st-loop. The CT SMASH architecture is implemented with several efficient circuit techniques suitable for high operation speed. As a result, the prototype fabricated in 28 nm CMOS achieves DR of 85 dB, peak SNDR of 74.9 dB, SFDR of 89.3 dBc, and Schreier FOM of 172.9 dB over a 50 MHz bandwidth at a 1.8 GHz sampling frequency.

• 出版日期2015-12