A sub-milliwatt audio-processing platform for digital hearing aids

作者：Yuan Jia^*; Chen Liming; Yu Zenghui; Hei Yong

来源：Chinese Journal of Semiconductors, 2014, 35(7): 075008.

DOI：10.1088/1674-4926/35/7/075008

• Application specific instruction-set processor
• Clock frequency
• Clock gating
• Digital hearing aids
• Hearing aid algorithms
• Instruction set
• Low Power
• Power reductions

We present a novel audio-processing platform, FlexEngine, which is composed of a 24-bit application-specific instruction-set processor (ASIP) and five dedicated accelerators. Acceleration instructions, compact instructions and repeat instruction are added into the ASIP's instruction set to deal with some core tasks of hearing aid algorithms. The five configurable accelerators are used to execute several of the most common functions of hearing aids. Moreover, several low power strategies, such as clock gating, data isolation, memory partition, bypass mode, sleep mode, are also applied in this platform for power reduction. The proposed platform is implemented in CMOS 130 nm technology, and test results show that power consumption of FlexEngine is 0.863 mW with the clock frequency of 8 MHz at Vdd = 1.0 V.

• 出版日期2014