摘要

In current reconfigurable compiling approach for solving affine subscript operations, the automatic generated feeding memory system is not optimal, especially to support an iteration pipeline structure. This paper presents a parameterized parallel memory template to mine parallelism and reusability of data, which is considered to address the lack of such aspect in reconfigurable compilers at hand. According to the analysis of characteristics of data access to affine subscript arrays in pipeline iteration, our template configures alternative sub-structures such as parallel multi-bank memory, sequential access memory, RAW Buffer and Smart Buffer. Furthermore, in phase of calculating parameter values to fill the template, the memory data dependence graph method is used, in which approach the flexibility of way to create memory structure is kept. The experimental result shows that compared with related works, the compiler can generate reconfigurable hardware performing a higher execution speed with less resources usage by employ the proposed memory template.

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