科研之友
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摘要
A fully integrated 79 to 87 GHz frequency synthesizer is proposed, which combines a W-band push-push 34 frequency multiplier and a K-band divider-less phase locked loop (PLL) with sampling phase detector. The circuit is verified in a standard 65 nm CMOS process. The frequency synthesizer consumes 54 mW totally, and the measured phase noise of divide-by-2 frequency is -100.1 and -106.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively.
- 出版日期2014-9
- 单位北京大学深圳研究生院; 北京大学
