科研之友
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摘要
This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches -6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40 similar to 54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 x 0.36 mm(2). The total power consumption is 16 mW.
- 出版日期2017-4-25
- 单位东南大学
