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摘要
This article summarizes the architectural design decisions of the hardware-accelerated low-power mote (halomote), which combines a field-programmable gate array for energy-efficient data aggregation with a radio system on chip for network management. The authors show halomote's power consumption improvements over typical software processors of wireless sensor networks for two use cases based on general data compression and application-specific feature extraction.
- 出版日期2016-12
