A 4 Bit Continuous-Time Sigma Delta Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer

作者：Briseno Vidrios Carlos^*; Edward Alexander; Rashidi Negar; Silva Martinez Jose

来源：IEEE Journal of Solid-State Circuits, 2016, 51(6): 1398-1409.

DOI：10.1109/JSSC.2016.2557809

• Analog-to-digital conversion
• cascaded ADC
• continuous-time sigma-delta modulators
• high-resolution ADCs
• low power ADC
• MASH ADC architectures
• multi bit quantizer
• subranging ADC

This paper presents a fully digital quantization noise reduction algorithm (DQNRA) for CT Sigma Delta M. The algorithm overcomes the signal leakage issues commonly found in cascade and MASH implementations. The proposed DQNRA is robust to PVT variations. The DQNRA performs a foreground measurement of the modulators noise transfer function. A Sigma Delta M using a 7 bit quantizer, from which the four most significant bits are used for the operation of the Sigma Delta M, proves the DQNRA concept. The remaining three least significant bits are used for the realization of the DQNRA for quantization noise improvement. A 7 bit quantizer with a three-step subranging architecture is implemented to reduce power and area consumption. A fourth-order continuous-time Sigma Delta prototype was implemented in 130 nm CMOS technology. The modulator's total power consumption is 20 mW, with only 6 mW used for the realization of the 7 bit quantizer operating at 500 MHz. For this prototype, the use of a DQNRA algorithm improved the modulator's SNDR from 69 to 75 dB over a 15 MHz bandwidth, limited after calibration by thermal noise rather than quantization noise. The obtained FoM is 164 dB.

• 出版日期2016-6