A 0.0055 mm(2) 480 mu W Fully Synthesizable PLL Using Stochastic TDC in 28 nm FDSOI

作者：Yang Dongsheng; Ueno Tomohiro; Deng Wei; Terashima Yuki; Nakata Kengo; Narayanan Aravind Tharayil; Wu Rui; Okada Kenichi; Matsuzawa Akira

来源：IEICE TRANSACTIONS ON ELECTRONICS, 2016, E99C(6): 632-640.

DOI：10.1587/transele.E99.C.632

• AD-PLL
• synthesizable
• stochastic TDC
• standard cell
• automatic place-and-route

A fully synthesizable all-digital phase-locked loop (AD-PLL) with a stochastic time-to-digital converter (STDC) is proposed in this paper. The whole AD-PLL circuit design is based on only standard cells from digital library, thus the layout of this AD-PLL can be automatically synthesized by a commercial place-and-route (P&R) tool with a foundry-provided standard-cell library. No manual layout and process modification is required in the whole AD-PLL design. In order to solve the delay mismatch issue in the delay-line-based time-to-digital converter (TDC), an STDC employing only standard D flip-flop (DFF) is presented to mitigate the sensitivity to layout mismatch resulted from automatic P&R. For the stochastic TDC, the key idea is to utilize the layout uncertainty due to automatic P&R which follows Gaussian distribution according to statistics theory. Moreover, the fully synthesized STDC can achieve a finer resolution compared to the conventional TDC. Implemented in a 28nm fully depleted silicon on insulator (FDSOI) technology, the fully synthesized PLL consumes only 480 mu W under 1.0V power supply while operating at 0.9GHz. It achieves a figure of merit (FoM) of -231.1dB with 4.0ps RMS jitter while occupying 0.0055 mm(2) chip area only.

• 出版日期2016-6