A 0.5-V 1.3-mu W Analog Front-End CMOS Circuit

作者：Zhu, Zhangming^*; Bai, Wenbin

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(6): 523-527.

DOI：10.1109/TCSII.2016.2530879

• Chopped capacitively coupled instrumentation amplifier (CCIA)
• front-end
• low power
• subthreshold
• successive-approximation analog-to-digital converter (SAR-ADC)
• switched capacitor filter (SC-filter)

This brief presents a low-power analog acquisition front-end circuit for a Wireless Body Area Network. This front-end system mainly consists of three parts, namely, chopped capacitively coupled instrumentation amplifier (CCIA), switched capacitor filter (SC-filter), and successive-approximation analog-to-digital converter. In order to reduce the power consumption, the supply voltage is scaled to 0.5 V, and all analog building blocks are biased in the subthreshold region. The chopper-stabilized technique is introduced to eliminate the 1/f noise, and a dc-servo loop is employed in the CCIA to suppress the electrode offset. A low-power second-order SC-filter is employed to eliminate the spikes produced by the CCIA, which also realizes a tunable gain to satisfy the specification. This low-power analog front-end circuit has been fabricated in a 0.18-mu m CMOS process. It occupies 1 mm(2) and consumes a minimal 1.3 mu W at 0.5 V. It achieves a bandwidth of 0.5-250 Hz, a CMRR of 95 dB, and an input impedance of 48 M Omega, respectively.

• 出版日期2016-6
• 单位西安电子科技大学