A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

作者：Kundu Sandipan^*; Alpman Erkan; Lu Julia Hsin Lin; Lakdawala Hasnain; Paramesh Jeyanandh; Jung Byunghoo; Zur Sarit; Gordon Eshel

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62(8): 1929-1939.

DOI：10.1109/TCSI.2015.2452372

• ADCs
• SAR
• semi-synchronous
• skew-tolerant
• switching-energy
• time-interleaving
• WiGig
• 802.11ad

A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a "correct-by-construction," timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44 dB EVM at sensitivity with a QAM16 signal.

• 出版日期2015-8