AN AGILE APPROACH TO BUILDING RISC-V MICROPROCESSORS

作者：Lee Yunsup^*; Waterman Andrew^*; Cook Henry^*; Zimmer Brian^*; Keller Ben^*; Puggelli Alberto^*; Kwak Jaehwa^*; Jevtic Ruzica^*; Bailey Stevo^*; Blagojevic Milovan^*; Chiu Pi Feng^*; Avizienis Rimas^*; Richards Brian^*; Bachrach Jonathan^*; Patterson David^*; Alon Elad^*; Nikolic Borivoje^*; Asanovic Krste^*

来源：IEEE Micro, 2016, 36(2): 8-20.

DOI：10.1109/mm.2016.11

THE AUTHORS ADOPTED AN AGILE HARDWARE DEVELOPMENT METHODOLOGY FOR 11 RISC-V MICROPROCESSOR TAPE-OUTS ON 28-NM AND 45-NM CMOS PROCESSES. THIS ENABLED SMALL TEAMS TO QUICKLY BUILD ENERGY-EFFICIENT, COST-EFFECTIVE, AND COMPETITIVE HIGH-PERFORMANCE MICROPROCESSORS. THE AUTHORS PRESENT A CASE STUDY OF ONE PROTOTYPE FEATURING A RISC-V VECTOR MICROPROCESSOR INTEGRATED WITH SWITCHED-CAPACITOR DC-DC CONVERTERS AND AN ADAPTIVE CLOCK GENERATOR IN A 28-NM, FULLY DEPLETED SILICON-ON-INSULATOR PROCESS.

• 出版日期2016-4