A Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCO

作者：Ho Yingchieh^*; Yang Yu Sheng; Chang ChiaChi; Su Chauchin

来源：IEEE Journal of Solid-State Circuits, 2013, 48(11): 2805-2814.

DOI：10.1109/JSSC.2013.2280409

• All-digital phase-locked loop (ADPLL)
• bootstrapped circuit
• energy-efficient design
• low-power
• low-voltage
• near-threshold circuit

This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm(2). The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 mu W. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 mu W (2.4 mu W) under a supply voltage of 0.5 V (0.25 V).

• 出版日期2013-11
• 单位东华大学