A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology

作者：Wang Huaide^*; Lee Jri

来源：IEEE Journal of Solid-State Circuits, 2010, 45(4): 909-920.

DOI：10.1109/JSSC.2010.2040117

• Analog equalizer
• decision-feedback equalizer (DFE)
• feedforward equalizer (FFE)
• transceiver (TRx)
• TSPC latch

A 21-Gb/s backplane transceiver has been presented. The transmitter incorporates half-rate topology with purely digital blocks to substantially reduce power consumption. The receiver employs analog and decision-feedback equalizers in a full-rate structure to avoid complicated structure. The one-tap decision-feedback equalizer merges the summer and the slicer into the flipflop, shortening the feedback path and speeding up the operation considerably. Fabricated in 65-nm CMOS, the transceiver (excluding clock generating PLL and CDR circuits) delivers 21-Gb/s data (2(31) - 1 PRBS) over 40-cm FR4 channel while consuming 87 mW from a 1.2-V supply.

• 出版日期2010-4