Multistage A(2)LVQ architecture and implementation for image compression

作者：Syafalni Infall; Salleh M F M^*

来源：Digital Signal Processing, 2013, 23(5): 1414-1426.

DOI：10.1016/j.dsp.2013.04.004

• A(2) lattice
• FPGA
• VLSI architecture
• Vector quantization

This paper presents the implementation of two hardware architectures, i.e., A(2) Lattice Vector Quantization (LVQ) and Multistage A(2)LVQ (MA(2)LVQ), using a Field-Programmable Gate Array (FPGA). First, the renowned LVQ quantizer by Conway and Sloane is implemented followed by a low-complexity A(2)LVQ based on a new A(2)LVQ algorithm. It is revealed that the implementation requires high number of multiplier circuits. Then the implementation of a low-complexity A(2)LVQ is presented. This implementation uses only the first quadrant of the A(2) lattice Voronoi region formed by W and T regions. This paper also presents the implementation of a multistage A(2)LVQ (MA(2)LVQ) with an architecture built from successive A(2) quantizer blocks. Synthesis results show that the execution time of the low-complexity A(2)LVQ reaches up to 35.97 ns. The MA(2)LVQ is implemented using both low-complexity A(2)LVQ and ordinary A(2) architectures. The system with the former architecture utilizes less logic and register elements by 47%.

• 出版日期2013-9