A 200 mu A Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS

作者：Drago Salvatore^*; Leenaerts Domine M W; Nauta Bram; Sebastiano Fabio; Makinwa Kofi A A; Breems Lucien J

来源：IEEE Journal of Solid-State Circuits, 2010, 45(7): 1305-1315.

DOI：10.1109/JSSC.2010.2049458

• CMOS
• duty-cycle
• frequency stability
• frequency synthesizer
• fully integrated
• PLL
• ultra-low-power
• wireless sensor networks
• WSN

The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 X 0.15 mm(2) and draws 200 mu A from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.

• 出版日期2010-7