A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device

作者：Tang Howard^*; Sun Zhuo Chao; Chew Kin Wai Roy; Siek Liter

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 23(10): 2220-2224.

DOI：10.1109/TVLSI.2013.2286393

• Analog-to-digital converter (ADC)
• asynchronous
• charge recycling
• dynamic comparator
• energy efficient
• low leakage
• low power
• medical implant
• successive approximation (SA)
• successive approximation register (SAR)

This brief presents a 10-bits successive approximation register analog-to-digital converter (ADC) with a sampling rate of 1 kS/s for implantable medical devices. This ADC is implemented in a 65-nm CMOS process in which leakage current will be a key design parameter. It imposes the highest degree of simplicity in the design of the ADCs architecture. Thus, the transistor count is minimized, which reduces not only the active power, but also the number of leakage sources. The modified top-plate V-cm-based switching offers energy efficient switching at the capacitive-DAC (CDAC) and uses simple control logic. In addition, the proposed asymmetrical metal-oxide-metal capacitor reduces the size of the CDAC by 90% for a given gain error. Furthermore, the input referred offset voltage of the dynamic comparator can be improved by the top-plate V-cm-based switching method at system level without using any additional transistor. The other building blocks are also simplified for lower power consumption. This ADC occupies an area of 0.046 mm(2). At 0.9 V and 1 kS/s, the 10-bits ADC consumes 5.8 nW, in which, 2.34 nW is contributed by leakage power consumption. The ADC achieves 9.1-ENOB and an energy efficiency of 10.94-fJ/conversion step.

• 出版日期2014-10
• 单位南阳理工学院