Embedded Deterministic Test Points

作者：Acero Cesar; Feltham Derek; Liu Yingdi; Moghaddam Elham; Mukherjee Nilanjan; Patyra Marek; Rajski Janusz; Reddy Sudhakar M; Tyszer Jerzy^*; Zawada Justyna

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(10): 2949-2961.

DOI：10.1109/TVLSI.2017.2717844

• Design for testability
• embedded test
• scan-based testing
• test application time
• test data compression
• test points

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2x-4x compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

• 出版日期2017-10