摘要

In order to reduce the power consumption of the touch screen control circuit, a low power successive approximation analog-to-digital converter (SAR ADC) was proposed. The capacitor array digital-to-analog converter (DAC). comparator and successive approximation register were studied and designed. Firstly, based on two-stage parallel-series capacitor, the capacitor array DAC and reference voltage switching scheme is designed. Next, two stage fully dynamic comparator is designed and the principle is analyzed. Then, based on the dynamic logic, successive approximation register with low power and low error code is designed. Finally, the ADC was implemented in 180 nm CMOS technology 1 V power supply and simulated at the input frequency Fin = 96.243 kHz and sampling frequency Fs = 200 kHz. The Simulation result indicates that values of Integral Non-Linearity(INL) and Differential Non-Linearity (DNL) are 0. 222/- 0. 203 LSB and 0.231/- 0.184 LSB respectively. Spurious Free Dynamic Range(SFDR) is 76.56 dB. Signal to Noise and Distortion Ratio is 61.50 dB. Effective Number of Bits(ENOB) is 9.92 bits. The power dissipation is only about 0.464 μW, figure of merit (FOM) is equal to 2.4 fJ/Conv.-step. In conclusion, the low power SAR ADC proposed in this paper meets the application requirement of touch screen control circuit.

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