A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL

作者：Kim Kyoung Ho^*; Bae Jun Han; Jun Young Hyun; Kwon Kee Won

来源：IEICE Electronics Express, 2014, 11(24): 20140828.

DOI：10.1587/elex.11.20140828

• clock and data recovery (CDR)
• phase-rotating PLL
• jitter characteristics
• split-tuned architecture

With a new phase-rotating phase locked loop (RPLL), a 5-Gbit/s quarter-rate clock and data recovery (CDR) circuit is presented in this brief. The RPLL employs a split-tuned architecture to decouple the tradeoff between RPLL bandwidth and power consumption. The uncertainty of phase interpolation due to the non-deterministic characteristics of the phase frequency detector (PFD) is eliminated by employing a PFD synchronizer (PFDS). Hence RPLL precisely performs seamless phase adjustment. The CDR, implemented in a digital 65 nm CMOS technology, shows 5.5-ps rms and 47.2-ps peak-to-peak jitter in the recovered clock and 10-12 bit error rate while consuming 10.3 mW from a 1.2-V supply.

• 出版日期2014