A Flexible DSP Architecture for MIMO Sphere Decoding

作者：Yang Chia Hsiang^*; Markovic Dejan

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2009, 56(10): 2301-2314.

DOI：10.1109/TCSI.2008.2012210

• CMOS digital integrated circuits
• diversity-multiplexing tradeoff
• flexible architecture
• multi-input-multi-output (MIMO) systems
• multidimensional signal processing
• sphere decoder
• wireless communications

This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequency subcarriers for orthogonal frequency-division multiplexing (OFDM) based systems. A 20 times area reduction is achieved, even without interleaving of subcarriers compared to the direct-mapped architecture. The sphere decoder supports multiple configurations: antenna arrays from 2 x 2 to 16 x 16, constellation sizes from binary phase-shift keying (BPSK) to 64-QAM (quadrature-amplitude modulation), and 16-128 subcarriers. The peak estimated data rate exceeds 1.5 Gbits/s of ideal throughput in a 16-MHz bandwidth. The core area is estimated at 0.31 mm(2) in a standard 90-nm CMOS technology. The estimated power consumption is 33 mW in the 16 x 16 64-QAM mode at 256 MHz from a 1-V supply voltage.

• 出版日期2009-10