An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

作者：Yoon Heung Sun^*; Park Jong Kang; Kim Jong Tae

来源：Journal of Semiconductor Technology and Science, 2015, 15(5): 445-454.

DOI：10.5573/JSTS.2015.15.5.445

• 3D-integrated SRAM
• soft error
• EDC
• ECC
• EDAC

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• 出版日期2015-10