科研之友
微信
新浪微博
Facebook
分享链接
摘要
A new readout circuit for MEMS devices is presented in this paper. A Phase Locked Loop (PLL) has been utilized to convert variations of MEM capacitance to time domain signals. The proposed scheme presents a robust performance against process, power supply and temperature variations due to inherent feedback of PLL systems. Simulation results in Cadence environment using TSMC CMOS 65-nm technology indicate that a measurement resolution of 73 aF can be achieved.
- 出版日期2012-10
