Achieving low-V-T Ni-FUSICMOS via lanthanide incorporation in the gate stack

作者：Veloso A^*; Yu H Y; Lauwers A; Chang S Z; Adelmann C; Onsia B; Demand M; Brus S; Vrancken C; Singanamalla R; Lehnen P; Kittl J; Kauerauf T; Vos R; O'; Sullivan B J; Van Elshocht S; Mitsuhashi R; Whittemore G; Yin K M; Niwa M; Hoffmann T; Absil P; Jurczak M; Biesemans S

来源：Solid-State Electronics, 2008, 52(9): 1303-1311.

DOI：10.1016/j.sse.2008.04.011

• Ni-FUSI metal gates
• work function modulation
• implanted dopants
• capping layers
• Low-V-T CMOS

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy2O3 Capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (I) both cases result in dielectric modification with gate leakage (J(C)) reduction; (2) adding a cap has no significant impact on T-inv(<1 angstrom), while Lip to similar to 5 and 2 angstrom reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest J(G) reduction (150x) is obtained for capped SiON devices due to dielectric intermixingand formation of a new high-k dielectric (DySiON), comparable to HfSiON in J(C) and mobility but with 500 mV smaller V-T: (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (V-T instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow Delta eWF(n-p) values Up to similar to 800 meV when combined with Ni-silicide FUSI phase engineering, promising for low-V-T CMOS.

• 出版日期2008-9