A Highly Efficient CMOS Envelope Tracking Power Amplifier Using All Bias Node Controls

作者：Jin Sangsu^*; Park Byungjoon; Moon Kyunghoon; Kim Jooseung; Kwon Myeongju; Kim Dongsu; Kim Bumman

来源：IEEE Microwave and Wireless Components Letters, 2015, 25(8): 517-519.

DOI：10.1109/LMWC.2015.2440652

• Adaptive bias
• CMOS
• differential
• envelope-tracking (ET)
• linearization
• LTE
• power amplifier (PA)

This letter presents a highly efficient CMOS power amplifier (PA) with adaptive envelope-tracking (ET) techniques. The linearity and efficiency of the PA are improved by ET-based techniques at the gate of the common-gate (CG), the gate of the common-source (CS), and the drain of the CG. The proposed CMOS ET PA is fabricated using a 0.18 mu m CMOS technology with a printed circuit board (PCB) transformer which has a lower insertion loss than CMOS one. Without any help of additional resources, the CMOS PA delivers an average output power of 27.5 dBm with a power-added efficiency (PAE) of 42.5%, an error vector magnitude (EVM) of 2.5%, and an ACLR(E-UTRA) of -36.5 dBc at 1.85 GHz for a long term evolution (LTE) signal with a bandwidth of 10 MHz and 7.5 dB peak-to-average power ratio (PAPR).

• 出版日期2015-8