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摘要
A novel zero-voltage and zero-current-switching (ZVZCS) full-bridge pulse-width modulation converter is proposed. The ZCS condition of the lagging-leg is obtained by a simple secondary auxiliary circuit resetting the primary current during the freewheeling stage. The auxiliary circuit's capacitor is charged by the center tape of the secondary through a diode, and the capacitor's voltage is clamped through another diode to output capacitor, thus, the voltage stress on the rectifier is clamped. There are neither additional active switches nor resistances in the auxiliary circuit, which makes the proposed converter efficient.
- 出版日期2005-3
- 单位四川大学
