摘要

In this article, a novel 90-nm gate length CMOS injection-locked frequency tripler that generates the 77 GHz output signal is proposed. The output signal frequency of proposed tripler could be locked precisely by using a one-third frequency local oscillator, which is beneficial for obtaining a wide tuning range and a low-phase-noise performance. In addition, the slow wave elevated-center coplanar waveguide transmission lines were adopted to reduce the chip size. The locked output frequency range is from 77.34 to 80.32 GHz together with a phase noise of -83.24 dBc/Hz at 1 MHz offset. The 0.81 mm(2) tripler (including passives) consumes 6.52 mW DC power under a 1.2 V voltage supply.

  • 出版日期2013-2
  • 单位长春大学

全文