A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing

作者：Zhang, Hong^*; Sun, Junqiang; Zhang, Jie; Zhang, Ruizhi; Carusone, Anthony Chan

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(9): 1763-1776.

DOI：10.1109/TVLSI.2018.2832472

• Boosted
• bucket-brigade device (BBD)
• low power
• pipelined-successive approximation register (SAR) analogto-digital converter (ADC)
• residue processing

A low-power pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) using boosted bucket-brigade device (BBD) for residue charge processing is presented. Boosted BBDs have been used as low-power and high-precision residue charge transfers in multistage pipelined ADCs, with drawbacks of large nonlinearity and severe accumulated common-mode (CM) charge error, which requires power-hungry real-time calibration circuits to control the CM level in each stage. When used in a two-stage pipelined-SAR ADC, only one boosted BBD pair is needed and its input signal range is attenuated remarkably by the first-stage SAR. Thus, zeropower power-up correction circuit can be used to stabilize the output CM level, and the nonlinear error of the boosted BBD is negligible. In addition, with top-plate sampling in the firststage SAR, two reference voltages for the conventional BBD are also eliminated. A proof-of-principle 10-bit two-stage pipelinedSAR ADC is implemented in a 0.18-mu m CMOS, showing an signal-to-noise-and-distortion ratio/spurious-free dynamic range of 57.1 dB/71A dB at 3.1-MHz input, while consuming 1.87 mW at 40 MS/s for a figure of merit of 78.9 fJ/step. The boosted BBD residue circuit consumes only 0.06 mW or 3% of the total power.

• 出版日期2018-9
• 单位西安交通大学