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摘要
This letter proposes a novel high performance crypto coprocessor that relies on Reconfigurable Cryptographic Blocks. We implement the prototype of the coprocessor on Xilinx FPGA chip. And the pipelining technique is adopted to realize data paralleling. The results show that the coprocessor, running at 189 MHz, outperforms the software-based SSL protocol.
- 出版日期2014-4
- 单位中国人民解放军国防科学技术大学
