摘要

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141nW to 188nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 mu V with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3-2.4mV (with input common mode range from 0V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1MHz in most process corners and temperature range of 0-100 degrees C which is suitable for most of the biomedical sensing applications.

  • 出版日期2015-10