摘要

This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13 mu m CMOS, the core of the neural compression and communication chip occupies only 1.21 mm(2) and consumes 800 mu W of power (25 mu W per channel at 26 KS/s) demonstrating an effective solution for intra-cortical neural interfaces.

  • 出版日期2014-4-30