A 10-Bit Self-Clocked SAR ADC With Enhanced Energy Efficiency for Multi-Sensor Applications

作者：Liu, Shubin; Shen, Yi; Wang, Jingyu; Zhu, Zhangming^*

来源：IEEE Sensors Journal, 2018, 18(10): 4223-4233.

DOI：10.1109/JSEN.2018.2822666

• SAR ADC
• self-clock
• automatic algorithm switching scheme (AASS)
• peak-to-peak jitter compensation

This paper presents a 10-bit self-clocked successive approximation analog-to-digital converter (SAR ADC) with enhanced energy efficiency suitable for multi-sensor applications. An automatic algorithm switching scheme possessing the high power efficiency advantages of both LSB-first SA and binary search algorithm is built with detecting the digital interval between two adjacent samplings to anticipate the switching scheme for subsequent sampling. To avoid the requirements for oscillator and clock generator, a self-clock circuit based on asynchronous timing is proposed, which can also serve as a sensor system clock. Furthermore, partial clock jitter compensation technology is added to compress the peak-to-peak jitter. The concepts of self-clock and full dynamic range high power efficiency make the SAR ADC well suited to sensor applications. Implemented in 0.18 mu m 1P6MCMOS process, the proposed ADC generates a 1.99-MHz clock signal with a peak-to-peak jitter of no more than 47.45 ps and achieves an SNDR of 57.7 dB and an SFDR of 68.9 dB with a 494.14-kHz sinusoidal input. The power dissipation is less than 9.3 mu W, corresponding to a figure of merit 7.5fJ/conversion step. The peak differential nonlinearity error is less than +0.22/-0.27 LSB and the peak integral nonlinearity error is no more than +0.52/-0.55LSB.

• 出版日期2018-5-15
• 单位西安电子科技大学