A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

作者：Shah Jaspal Singh^*; Nairn David; Sachdev Manoj

来源：IEEE Transactions on Nuclear Science, 2015, 62(3): 1367-1374.

DOI：10.1109/TNS.2015.2429589

• Hardened by design (HBD)
• single-event upset (SEU)
• soft-error rate (SER)
• soft-error robust
• SRAM

A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T cell does not have dedicated access transistors, and its quad-latch configuration stores data on four interlocked storage nodes. The macro was designed in a 65-nm CMOS process. The cell demonstrates excellent read data stability down to 0.55 V and is well suited for low-voltage, low-power applications. Neutron radiation testing on the macro exhibits at least 15x improvement in Failure in Time (FIT) rate compared with the conventional 6T SRAM cell in 65-nm CMOS technology.

• 出版日期2015-6