Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding

作者：Ko, Hou Jen^*; Hsiao, Shen Fu

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2011, 58(5): 304-308.

DOI：10.1109/TCSII.2011.2148970

• Computer arithmetic
• faithful rounding
• fixed-width multiplier
• tree reduction
• truncated multiplier

A faithfully rounded truncated multiplier design is presented where the maximum absolute error is guaranteed to be no more than 1 unit of least position. The proposed method jointly considers the deletion, reduction, truncation, and rounding of partial product bits in order to minimize the number of full adders and half adders during tree reduction. Experimental results demonstrate the efficiency of the proposed faithfully truncated multiplier with area saving rates of more than 30%. In addition, the truncated multiplier design also has smaller delay due to the smaller bit width in the final carry-propagate adder.

• 出版日期2011-5
• 单位中山大学