A fast, low-power, 6-bit SAR ADC for readout of strip detectors in the LHCb Upgrade experiment

作者：Firlej M; Fiutowski T; Idzik M^*; Moron J; Swientek K

来源：Journal of Instrumentation, 2014, 9(07): P07006.

DOI：10.1088/1748-0221/9/07/P07006

• VLSI circuits
• Analogue electronic circuits
• Digital electronic circuits
• Front-end electronics for detector readout

The readout of silicon strip sensors in the upgraded Tracker System of Large Hadron Collider beauty (LHCb) experiment will require a novel complex Application Specific Integrated Circuit (ASIC). The ASIC will extract and digitise analogue signal from the sensor and subsequently will perform digital processing and serial data transmission. One of the key processing blocks, placed in each channel, will be an Analogue to Digital Converter (ADC). A prototype of fast, low-power 6-bit Successive Approximation Register (SAR) ADC was designed, fabricated and tested. The measurements of ADC prototypes confirmed simulation results showing excellent overall performance. In particular, very good resolution with Effective Number Of Bits (ENOB) 5.85 was obtained together with very low power consumption of 0.35 mW at 40 MS/s sampling rate. The results of the performed static and dynamic measurements confirm excellent ADC operation for higher sampling rates up to 80 MS/s.

• 出版日期2014-7