A Low Cost Design of Hardware Support for On-chip Message Passing in Manycore Processors

作者:Han, Xing*; Fu, Yuzhuo; Jiang, Jiang
来源:IEEE 6th International Conference on Electronics Information and Emergency Communication (ICEIEC), 2016-06-17 To 2016-06-19.
DOI:10.1109/ICEIEC.2016.7589749

摘要

In this paper, we propose a low cost hardware support for on-chip message passing mechanism in manycore processors. Data sharing is an important problem for manycore processor. As the scale of manycore processors increases, the penalty of multicasts from cache coherence protocol increases dramatically, which restricts the performance of on-chip communications. In order to improve the performance of inter-core communications, message passing is introduced into manycore processors. On-chip message passing buffers are designed to supply high performance message passing in manycore processors, which takes about 5.26% on-chip storage area. However, the utilization of on-chip storage is low due to the usage of lightweight cores in manycore processors, in which computing and data transmission will not work simultaneously. This paper proposes a message passing scheme via reusing the cache memories and logical circuits in state machine from original cache coherence protocols. With reusing of cache memories, only 0.01% overhead in hardware costs are required to gain the similar performance with original message passing design. And our design with the same hardware costs gains 11% improvements in overall performance.

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