A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing

作者：Aniruddhan Sankaran^*; Shekhar Sudip; Allstot David J

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2011, 58(5): 860-867.

DOI：10.1109/TCSI.2010.2090565

• Dual-loop phase-locked loop (PLL)
• even-harmonic mixer
• frequency synthesizer
• voltage-controlled oscillator

A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18-mu m CMOS locks in 40 mu s and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1 degrees and the phase noise spectral density is -116.8 dBc/Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are -83 dBc and -105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively.

• 出版日期2011-5