A 5.25-V-tolerant bidirectional I/O circuit in a 28-nm CMOS process

作者：Ahn Keun Seon; Park Jae Woo; Yoo Changsik^*

来源：International Journal of Circuit Theory and Applications, 2015, 43(6): 822-828.

DOI：10.1002/cta.1981

• I
• O circuit
• voltage stress
• bidirectional I
• O
• CMOS

A 5.25-V-tolerant bidirectional I/O circuit has been developed in a 28-nm standard complementary metal-oxide-semiconductor (CMOS) process with only 0.9 and 1.8V transistors. The transistors of the I/O circuit are protected from over-voltage stress by cascode transistors whose gate bias level is adaptively controlled according to the voltage level of the I/O pad. The n-well bias level of the p-type metal-oxide-semiconductor transistors of the I/O circuit is also adapted to the voltage level of the I/O pad to prevent any junction leakage. The 5.25-V-tolerant bidirectional I/O circuit occupies 40 mu mx170 mu m of silicon area.

• 出版日期2015-6