A 1.3V input fast-transient-response time digital low-dropout regulator with a VSSa generator for DVFS system

作者：Min Young Jae^*; Jeong Chan Hui; Moon Junil; Han Youngsun; Kim Soo Won; Kim Chulwoo

来源：IEICE Electronics Express, 2017, 14(13): 20170461.

DOI：10.1587/elex.14.20170461

• low-dropout (LDO) regulator
• digital low-dropout (D-LDO) regulator
• fast-transient-response time
• dynamic voltage frequency scaling (DVFS)

A fast transient-response digital low-dropout regulator ( D-LDO) is presented. To achieve fast-transient time, a VSSa generator and a coarse-fine power-MOS array techniques are proposed. The proposed D-LDO is implemented in a 65 nm CMOS technology with a die area of 0.067 mm(2). The measured recovery time is less than 0.32 us when the load step-up time is 0.1 us from 2.5mA to 120 mA, and the step-down time is 0.1 us at 1.2V of supply voltage. Moreover, the voltage spikes are less than 190mV.

• 出版日期2017-7-10