A New Readout Circuit Structure for SAR Satellite Imaging Sensors

作者：Rezai Rad Gholam Ali^*; Akbarizadeh Gholamreza

来源：International Review of Electrical Engineering, 2010, 5(1): 281-290.

• Synthetic Aperture Radar
• Readout Circuit
• Readout Electronics
• SAR Imaging Systems
• Satellite

In this paper we propose and design a new CMOS readout circuit for high-resolution Synthetic Aperture Radar imaging system. This CMOS readout circuit is designed for Gallium Nitride detector with P V type and it is simulated in transistor level and its physical layout is also drawn. The detector of this circuit works in Microwave-Radar length. This structure can simultaneously provide high (azimuth) resolution and wide coverage (swath) and it has Smart Multi Aperture Radar technology. Substance of material in this circuit is GaN. Recent development in semiconductor technology, specifically Gallium Nitride, allows handling significantly higher amount of peak power and be this prove to be an attractive solution to increase the echo window length without sacrificing average transmit power and SNR. To provide stable bias voltage across the photo detector diode, we use a feedback structure with current mirrors in our scheme, while mirroring the diode current to an integration capacitor. In this circuit, the integration capacitor is placed outside of the unit pixel. This technique used in the circuit structure, reduces the pixel area and allows integrating the current on larger capacitance for larger charge storage capacity and dynamic range. One of the greater properties of current feedback in this structure is that, very low (ideally zero) input impedance is achieved. The unit-cell which we designed and proposed contains just nine MOS transistors and occupies 30 micro meters by 30 micro meters area in a 0.35 micro-meter CMOS process. This circuit has 10 MHz maximum readout speed, a linearity of 99.55%, a power dissipation of 150nW for 1 cell and 50mW for test chip, a voltage swing of 2.8v, an injection efficiency of 100% and provides a maximum charge storage capacity of 1 x 10(7) electrons. This readout circuit has 1pF off-pixel integration capacitor for a 3.3 V power supply. The chip layout of this circuit was designed in a 0.35 mu m standard N-well CMOS process which shows that each Pixel of this circuit occupies 1.95mm(2) of silicon area. This portable chip is very useful to use on SA R satellites.

• 出版日期2010-2