A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches

作者：Chun Ki Chul^*; Jain Pulkit; Kim Tae Ho; Kim Chris H

来源：IEEE Journal of Solid-State Circuits, 2012, 47(2): 547-559.

DOI：10.1109/JSSC.2011.2168729

• Cache
• logic-compatible eDRAM
• random cycle
• sense amplifier
• 2T gain cell

Circuit techniques for enhancing the retention time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to maintain a high data '1' voltage level which enables fast read access using an NMOS read device. A current-mode sense amplifier (C-S/A) featuring a cross-coupled PMOS latch and pseudo-PMOS diode pairs is proposed to overcome the innate problem of small read bit-line (RBL) voltage swing in 2T eDRAMs with improved voltage headroom and better impedance matching under process-voltage-temperature (PVT) variations. A half-swing write bit-line (WBL) scheme is adopted to improve the WBL speed by 33% and reduce its power dissipation by 25% during write-back operation with no effect on retention time. A stepped write word-line (WWL) driver reduces the current drawn from the boosted high and low supplies by 67%. A 192 kb eDRAM test chip with 512 cells-per-BL implemented in a 65 nm low-power (LP) CMOS process shows a random cycle frequency and latency of 667 MHz and 1.65 ns, respectively, at 1.1 V and 85 C. The measured refresh period at a 99.9% bit yield condition was 110 mu s which is comparable to that of recently published 1T1C eDRAM designs.

• 出版日期2012-2