An Accurate Fractional Period Delay Generation System

作者：Das Pratap Kumar^*; Amrutur Bharadwaj

来源：IEEE Transactions on Instrumentation and Measurement, 2012, 61(7): 1924-1932.

DOI：10.1109/TIM.2011.2182249

• Accuracy
• asynchronous subsampling
• clock skew measurement
• delay locked loop (DLL)
• differential nonlinearity (DNL)
• digital-to-phase converter (DPC)
• field programmable gate array (FPGA)
• integral nonlinearity (INL)
• phase-locked loop (PLL)
• precision
• programmable delay generator
• programmable phase generator
• time-to-digital converter (TDC)

An all-digital technique is proposed for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A subsampling technique-based delay measurement unit (DMU) capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The proposed delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. Up to 40x improvement in accuracy is demonstrated for a commercial programmable delay generator chip. The time-precision trade-off feature of the DMU is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter. Measurement results from a high-end oscilloscope also validate the effectiveness of the proposed system in improving accuracy.

• 出版日期2012-7