A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method

作者：Mantyniemi Antti^*; Rahkonen Timo; Kostamovaara Juha

来源：IEEE Journal of Solid-State Circuits, 2009, 44(11): 3067-3078.

DOI：10.1109/JSSC.2009.2032260

• All-digital delay-locked loop (ADDLL)
• CMOS integrated circuits
• delay line interpolation
• delay-locked loop (DLL)
• digital-to-time converter (DTC)
• successive approximation register (SAR)
• time digitizer
• time interval measurement
• time-to-digital converter (TDC)

This paper describes a time-to-digital converter (TDC) with similar to 1.2 ps resolution and similar to 327 mu s dynamic range suitable for laser range-finding application for example. The resolution of similar to 1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation sigma-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 m CMOS process.

• 出版日期2009-11